NRF54L15 setting pin 2.07 as UART TX does not work

Question

I am on a custom NRF54L15 module where I want to change the default UART TX pin from P1.04 to P2.07. Unfortunately, there is no output. Using P1.14 somehow works?
I also have MCU Boot enabled when I connect my wires to pin P1.04 I see the MCU Boot logs, but not the one from my main app - as expected because they should be printed to P2.07 but thats not working as said ...

My overlay:

/ {
    zephyr,user {
        //epd_test_gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; // NOT WORKING
        led_builtin_gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
        io-channels = <&adc 0>, <&adc 1>;
        /*
        epd_busy_gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
        epd_res_gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
        epd_dc_gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
        epd_cs_gpios = <&gpio1 00 GPIO_ACTIVE_LOW>;
         */
        // epd_spi_clk_gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
        // epd_spi_mosi_gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; // SDI
    };

    aliases {
        /delete-property/ sw3;
        /delete-property/ led3;
        /delete-property/ sw2;
        /delete-property/ sw1;
        /delete-property/ sw0;
    };
};


/delete-node/ &button3;
/delete-node/ &{/buttons/};
/delete-node/ &led3;

&led1 {
    gpios = <&gpio1 6 0>;
};

&led2 {
    gpios = <&gpio1 5 0>;
};




&cpuapp_rram {
    reg = <0x0 DT_SIZE_K(1524)>;
};

&cpuapp_sram {//! Without this the only 188Kb of RAM is available
    reg = <0x20000000 DT_SIZE_K(256)>;
    ranges = <0x0 0x20000000 DT_SIZE_K(256)>;
};

&adc {
    #address-cells = <1>;
    #size-cells = <0>;

    channel@0 {
        reg = <0>;
        zephyr,gain = "ADC_GAIN_1_6";
        zephyr,reference = "ADC_REF_VDD_1";
        zephyr,acquisition-time = <0>;
        zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
        zephyr,resolution = <10>;
    };

};

&spi00_default {
    group1 {
        psels = <NRF_PSEL(SPIM_SCK, 2, 6)>, <NRF_PSEL(SPIM_MOSI, 0, 10)>;           // (SPIM_MOSI, 1, 6)    // (SPIM_MOSI, 1, 11)
    };
};

&spi00_sleep {
    group1 {
        psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
                <NRF_PSEL(SPIM_MOSI, 0, 10)>;
    };
};

&pinctrl {
    uart20_default: uart20_default {
        group1 {
            psels = <NRF_PSEL(UART_TX, 2, 7)>,
                    <NRF_PSEL(UART_RTS, 2, 8)>;
        };
        group2 {
            psels = <NRF_PSEL(UART_RX, 2, 9)>,
                    <NRF_PSEL(UART_CTS, 2, 10)>;
            bias-pull-up;
        };
    };

    uart20_sleep: uart20_sleep {
        group1 {
            psels =
                <NRF_PSEL(UART_TX, 2, 7)>,
                <NRF_PSEL(UART_RTS, 2, 8)>,
                <NRF_PSEL(UART_RX, 2, 9)>,
                <NRF_PSEL(UART_CTS, 2, 10)>;
            low-power-enable;
        };
    };
};

&uart20 {
    status = "okay";
    current-speed = <115200>;
    pinctrl-0 = <&uart20_default>;
    pinctrl-1 = <&uart20_sleep>;
    pinctrl-names = "default", "sleep";
};


/delete-node/ &boot_partition;
/delete-node/ &slot0_partition;
/delete-node/ &slot1_partition;
/ {
    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        boot_partition: partition@0 {
            label = "mcuboot";
            reg = <0x00000 0x0C000>;
        };

        pad_partition: partition@c000 {
            label = "mcuboot_pad";
            reg = <0x0C000 0x200>;
        };

        slot0_partition: partition@c200 {
            label = "mcuboot_primary";
            reg = <0x0C200 0x40000>;
        };

        slot1_partition: partition@4c200 {
            label = "mcuboot_secondary";
            reg = <0x4C200 0x40000>;
        };

        nvs_partition: partition@8c200 {
            label = "nvs_storage";
            reg = <0x8C200 0x6BE00>;
        };

    };
};

Thanks

Syed Maysum Abbas Zaidi · Accepted Answer

Hi, 
 You are most likely not able to use P2.07 as a UART TX pin due to the pin-mapping limitations described in the nRF54L15 documentation. As stated in the UART Documentation , the UART20 instance can use any pin on GPIO port P1, but when using GPIO port P2, only the dedicated pins listed in the Pin Assignment Table can be used. According to the pin assignment table, P2.07 is not TX-capable. It can only be used as a UART RX pin, and only for specific UART instances (UARTE00/21). Another thing to keep in mind is that when a PERI-domain peripheral (such as UARTE20/21/22) uses pins in the MCU domain (P2), the device must operate in Constant Latency sub-power mode. In Zephyr, this can be done by adding CONFIG_NRF_SYS_EVENT=y in the Kconfig and calling nrf_sys_event_request_global_constlat() while the cross‑domain UART is in use. Moreover remember to optionally go back to low‑power mode when you are done with the UART by calling nrf_sys_event_release_global_constlat(). But before this you must ensure that specific pin is actually a valid pin for that UART instance. For further details regarding pin assignments you can have a look at this blog post: Pin Assignment Guidlines Best Regards, Syed Maysum

NRF54L15 setting pin 2.07 as UART TX does not work

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