SDK 3.1.0 Serial recovery appcore + netcore

Question

Hello,

I have followed the guide to do a serial recovery of the appcore and it's working fine. Now I would like to be able to update both the appcore and the netcore.

I have configured my project as follow:

sysbuild.conf

SB_CONFIG_BOOTLOADER_MCUBOOT=y

# use hci ipc as netcore child image
SB_CONFIG_NETCORE_HCI_IPC=y

# use netcore bootloader as child image
# secure bootloader is required for netcore bootloader see:
# https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/samples/nrf5340/netboot/README.html#building_and_running
SB_CONFIG_SECURE_BOOT_NETCORE=y

# secure boot on appcore doesn't seem to be required
SB_CONFIG_SECURE_BOOT_APPCORE=n

# required to update netcore image from appcore using mcuboot
SB_CONFIG_NETCORE_APP_UPDATE=y

# one image pair mode without scratch partition
SB_CONFIG_MCUBOOT_NRF53_MULTI_IMAGE_UPDATE=n
SB_CONFIG_MCUBOOT_UPDATEABLE_IMAGES=1
SB_CONFIG_MCUBOOT_MODE_SINGLE_APP=y

# Match MCUboot signing type with keys/appcore_debug_mcuboot_private.pem (EC P-256)
SB_CONFIG_BOOT_SIGNATURE_TYPE_ECDSA_P256=y 
 mcuboot.conf CONFIG_FLASH=y

# serial recovery
CONFIG_MCUBOOT_SERIAL=y
CONFIG_BOOT_SERIAL_UART=y
CONFIG_BOOT_SERIAL_ENTRANCE_GPIO=n
CONFIG_BOOT_SERIAL_WAIT_FOR_DFU=y
CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT=500
CONFIG_BOOT_SERIAL_NO_APPLICATION=y
CONFIG_BOOT_SERIAL_BOOT_MODE=y

# boot mode retention
CONFIG_RETENTION=y
CONFIG_RETAINED_MEM=y
CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
CONFIG_RETENTION_BOOT_MODE=y

# serial recovery netcore
CONFIG_BOOT_IMAGE_ACCESS_HOOKS=y
CONFIG_FLASH_SIMULATOR=y
CONFIG_FLASH_SIMULATOR_DOUBLE_WRITES=y
CONFIG_FLASH_SIMULATOR_STATS=n
CONFIG_MCUBOOT_SERIAL_DIRECT_IMAGE_UPLOAD=y
CONFIG_NRF53_RECOVERY_NETWORK_CORE=y

CONFIG_PCD_APP=y

# Decrease memory footprint
CONFIG_SIZE_OPTIMIZATIONS=y
CONFIG_CBPRINTF_NANO=y
CONFIG_TIMESLICING=n
CONFIG_BOOT_BANNER=n
CONFIG_CONSOLE=n
CONFIG_CONSOLE_HANDLER=n
CONFIG_UART_CONSOLE=n
CONFIG_USE_SEGGER_RTT=n
CONFIG_LOG=n
CONFIG_ERRNO=n
CONFIG_PRINTK=n prj.conf CONFIG_MPSL_PIN_DEBUG=y

# Some command handlers require a large stack.
CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
CONFIG_MAIN_STACK_SIZE=4096

# Current implementation of UART uses k_malloc and
# therefore, heap must be >0 ...
CONFIG_HEAP_MEM_POOL_SIZE=4096

# Required by the `taskstat` command.
CONFIG_THREAD_MONITOR=y
CONFIG_THREAD_NAME=y

# Enable statistics and statistic names.
CONFIG_STATS=y
CONFIG_STATS_NAMES=y

# Assert
CONFIG_ASSERT=y
CONFIG_HW_STACK_PROTECTION=y

# Bluetooth config
CONFIG_BT=y
CONFIG_BT_HCI_RAW=y
CONFIG_BT_HCI_RAW_H4=y
CONFIG_BT_HCI_RAW_H4_ENABLE=y
CONFIG_BT_BUF_ACL_TX_COUNT=8
CONFIG_BT_BUF_ACL_TX_SIZE=256
CONFIG_BT_BUF_ACL_RX_COUNT=8
CONFIG_BT_BUF_ACL_RX_SIZE=256
CONFIG_BT_ISO_BROADCASTER=y
CONFIG_BT_ISO_CENTRAL=y
CONFIG_BT_ISO_MAX_CHAN=2

# IPC
CONFIG_IPC_SERVICE=y
CONFIG_IPC_SERVICE_BACKEND_RPMSG=y

# Audio codec LC3 related defines
# FPU_SHARING enables preservation of the hardware floating point registers
# across context switches to allow multiple threads to perform concurrent
# floating point operations.
CONFIG_FPU=y
CONFIG_FPU_SHARING=y

# NOTE: Since we are not using minimal libc, error codes from
# minimal libc are not used
CONFIG_NEWLIB_LIBC=y

# I2S
CONFIG_NRFX_I2S0=y

# Enable the data first-in first-out library
CONFIG_DATA_FIFO=y

# Library for manipulating pulse coded modulation (PCM) streams
CONFIG_PSCM=y

# Configure UART async correctly
CONFIG_SERIAL=y
CONFIG_UART_ASYNC_API=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_0_INTERRUPT_DRIVEN=n
CONFIG_UART_1_INTERRUPT_DRIVEN=n
CONFIG_UART_0_ASYNC=y
CONFIG_UART_1_ASYNC=y
CONFIG_NRFX_UARTE0=y
CONFIG_NRFX_UARTE1=y
CONFIG_UART_NRFX_UARTE_ENHANCED_RX=y
CONFIG_UART_USE_RUNTIME_CONFIGURE=y

# Audio sync timer
CONFIG_NRFX_TIMER1=y

# Boot mode
CONFIG_RETENTION=y
CONFIG_RETAINED_MEM=y
CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
CONFIG_RETENTION_BOOT_MODE=y
CONFIG_REBOOT=y

# Enable PSA Crypto with hardware acceleration
CONFIG_PSA_CRYPTO_DRIVER_CC3XX=y
CONFIG_PSA_CRYPTO_DRIVER_OBERON=n

# Enable CryptoCell CC312 hardware
CONFIG_HW_CC3XX=y
CONFIG_CC3XX_BACKEND=y

# Enable nordic security backend and PSA APIs
CONFIG_NRF_SECURITY=y
CONFIG_MBEDTLS_PSA_CRYPTO_C=y

CONFIG_PSA_WANT_ALG_ECDH=y
CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE=y
CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT=y
CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT=y
CONFIG_PSA_WANT_ECC_SECP_R1_256=y
CONFIG_PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY=y

# For key generation
CONFIG_PSA_WANT_GENERATE_RANDOM=y

CONFIG_MBEDTLS_ENABLE_HEAP=y
CONFIG_MBEDTLS_HEAP_SIZE=16384 
 
 I have a partition manager applied as follow: flash_primary (0x100000 - 1024kB):
+--------------------------------------------------+
+---0x0: b0_container (0x8000 - 32kB)--------------+
| 0x0: b0 (0x8000 - 32kB) |
+---0x8000: s0 (0xc000 - 48kB)---------------------+
| 0x8000: s0_pad (0x200 - 512B) |
+---0x8200: s0_image (0xbe00 - 47kB)---------------+
| 0x8200: mcuboot (0xbe00 - 47kB) |
+--------------------------------------------------+
| 0x14000: EMPTY_0 (0x4000 - 16kB) |
+---0x18000: s1 (0xc000 - 48kB)--------------------+
| 0x18000: s1_pad (0x200 - 512B) |
| 0x18200: s1_image (0xbe00 - 47kB) |
+--------------------------------------------------+
| 0x24000: EMPTY_1 (0x4000 - 16kB) |
+---0x28000: mcuboot_primary (0x6c000 - 432kB)-----+
| 0x28000: mcuboot_pad (0x200 - 512B) |
+---0x28200: app_image (0x6be00 - 431kB)-----------+
+---0x28200: mcuboot_primary_app (0x6be00 - 431kB)-+
| 0x28200: app (0x6be00 - 431kB) |
+--------------------------------------------------+
| 0x94000: mcuboot_secondary (0x6c000 - 432kB) |
| 0xb8000: mcuboot_secondary_1 (0x40000 - 256kB) |
| 0xf8000: settings_storage (0x8000 - 32kB) |
+--------------------------------------------------+

 otp (0x2fc - 764B):
+------------------------------+
| 0xff8100: otp (0x2fc - 764B) |
+------------------------------+

 ram_flash (0x40000 - 256kB):
+------------------------------------------+
| 0x0: mcuboot_primary_1 (0x40000 - 256kB) |
| 0x40000: ram_flash (0x0 - 0B) |
+------------------------------------------+

 sram_primary (0x3ffff - 255kB):
+-----------------------------------------------+
| 0x20000000: pcd_sram (0x2000 - 8kB) |
| 0x20002000: sram_retained_mem (0x400 - 1kB) |
| 0x20002400: sram_primary (0x2dbff - 182kB) |
| 0x2002ffff: rpmsg_nrf53_sram (0x10000 - 64kB) |
+-----------------------------------------------+

 CPUNET flash_primary (0x40000 - 256kB):
+--------------------------------------------+
+---0x1000000: b0n_container (0x8800 - 34kB)-+
| 0x1000000: b0n (0x8580 - 33kB) |
| 0x1008580: provision (0x280 - 640B) |
+---0x1008800: app (0x37800 - 222kB)---------+
| 0x1008800: hci_ipc (0x37800 - 222kB) |
+--------------------------------------------+

 CPUNET sram_primary (0x10000 - 64kB):
+-------------------------------------------+
| 0x21000000: sram_primary (0x10000 - 64kB) |
+-------------------------------------------+ The problem is that the ram is overflowed by a lot due to the mock_flash partition: -- Zephyr version: 4.1.99 (/workspace/_nordic_sdk/zephyr), build: ff8f0c579eeb
[202/207] Linking C executable zephyr/zephyr_pre0.elf
FAILED: zephyr/zephyr_pre0.elf zephyr/zephyr_pre0.map /workspace/_obj/app/baseband_nordic/sdk_3_1/mezza_nordic/mcuboot/zephyr/zephyr_pre0.map
: && ccache /opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gcc -gdwarf-4 zephyr/CMakeFiles/zephyr_pre0.dir/misc/empty_file.c.obj -o zephyr/zephyr_pre0.elf zephyr/CMakeFiles/offsets.dir/./arch/arm/core/offsets/offsets.c.obj -T zephyr/linker_zephyr_pre0.cmd -Wl,-Map=/workspace/_obj/app/baseband_nordic/sdk_3_1/mezza_nordic/mcuboot/zephyr/zephyr_pre0.map -Wl,--whole-archive app/libapp.a zephyr/libzephyr.a zephyr/arch/common/libarch__common.a zephyr/arch/arch/arm/core/libarch__arm__core.a zephyr/arch/arch/arm/core/cortex_m/libarch__arm__core__cortex_m.a zephyr/arch/arch/arm/core/cortex_m/cmse/libarch__arm__core__cortex_m__cmse.a zephyr/arch/arch/arm/core/mpu/libarch__arm__core__mpu.a zephyr/lib/libc/picolibc/liblib__libc__picolibc.a zephyr/lib/libc/common/liblib__libc__common.a zephyr/soc/soc/nrf5340/libsoc__nordic.a zephyr/boards/boards/arm/mezza_nordic/lib..__..__modules__phc_boards__boards__sonova__mezza_nordic.a zephyr/subsys/retention/libsubsys__retention.a zephyr/drivers/clock_control/libdrivers__clock_control.a zephyr/drivers/flash/libdrivers__flash.a zephyr/drivers/gpio/libdrivers__gpio.a zephyr/drivers/pinctrl/libdrivers__pinctrl.a zephyr/drivers/regulator/libdrivers__regulator.a zephyr/drivers/retained_mem/libdrivers__retained_mem.a zephyr/drivers/serial/libdrivers__serial.a zephyr/drivers/timer/libdrivers__timer.a modules/nrf/lib/fprotect/lib..__nrf__lib__fprotect.a modules/nrf/subsys/pcd/lib..__nrf__subsys__pcd.a modules/nrf/modules/mcuboot/hooks/lib..__nrf__modules__mcuboot__hooks.a modules/nrf/drivers/hw_cc3xx/lib..__nrf__drivers__hw_cc3xx.a modules/mcuboot/boot/bootutil/zephyr/libmcuboot_util.a modules/hal_nordic/modules/hal_nordic/nrfx/libmodules__hal_nordic__nrfx.a modules/zcbor/libmodules__zcbor.a -Wl,--no-whole-archive zephyr/kernel/libkernel.a -L/workspace/_obj/app/baseband_nordic/sdk_3_1/mezza_nordic/mcuboot/zephyr zephyr/arch/common/libisr_tables.a -mcpu=cortex-m33 -mthumb -mabi=aapcs -mfp16-format=ieee -mtp=soft -fuse-ld=bfd -Wl,--gc-sections -Wl,--build-id=none -Wl,--sort-common=descending -Wl,--sort-section=alignment -Wl,-u,_OffsetAbsSyms -Wl,-u,_ConfigAbsSyms -nostdlib -static -Wl,-X -Wl,-N -Wl,--orphan-handling=warn -Wl,-no-pie -specs=picolibc.specs -DPICOLIBC_MINIMAL_PRINTF_SCANF /workspace/_nordic_sdk/nrfxlib/crypto/nrf_cc312_platform/lib/cortex-m33/soft-float/no-interrupts/libnrf_cc312_platform_0.9.19.a -L"/opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/thumb/v8-m.main/nofp" -lc -lgcc && cd /workspace/_obj/app/baseband_nordic/sdk_3_1/mezza_nordic/mcuboot/zephyr && /opt/ncs/toolchains/b2ecd2435d/usr/local/bin/cmake -E true
/opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: zephyr/zephyr_pre0.elf section `bss' will not fit in region `RAM'
/opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: region `RAM' overflowed by 91745 bytes I have followed these guides: MCUboot’s serial recovery of the networking core image nRF5340: Network core bootloader Any idea what is wrong? The AI suggest to reduce the size of the sim_flash to fit only the hci_ipc image and effectively some memory are spared: /opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: zephyr/zephyr_pre0.elf section `bss' will not fit in region `RAM'
/opt/ncs/toolchains/b2ecd2435d/opt/zephyr-sdk/arm-zephyr-eabi/bin/../lib/gcc/arm-zephyr-eabi/12.2.0/../../../../arm-zephyr-eabi/bin/ld.bfd: region `RAM' overflowed by 58977 bytes 
 
 But I still need to spare ~58k

Cyril Praz · Accepted Answer

I have found my problem and it was simply that I have copy paste blindly from this guide: Retention System the following line: /* Reduce SRAM0 usage by 1 byte to account for non-init area */ &sram0 { reg = <0x20000000 0x3FFFF>; }; The problem is that by doing that I have not only removed 1 byte but ~256Kb of RAM. From this change everything started to be messy and the partition manager becoming to be out of sync from the dts configuration. Several things that I have learned the hard way and is maybe important to mention here are the following points: rpmsg_nrf53_sram is automatically created by nordic but only the size is taken from the dts not the position. Make sure to check that the partition start address match the reserved memory sram0_shared The compilation of the nordic firmware is based sometimes on partition_manager and sometimes on the dts configuration. Changing the position of a partition inside pm_static.yml will not necessarily have the intended effect. If the compilation fail due to a linker error one solution may be to fix the problem is to remove the pm_static.yml file and look what changed as I said sometimes some fields inside pm_static depend on the project configuration and cant be modified directly isnide pm_static.yml Here is the configuration that I have at the end for who is interested: prj.conf: # Boot mode CONFIG_RETENTION=y CONFIG_RETAINED_MEM=y CONFIG_RETAINED_MEM_ZEPHYR_RAM=y CONFIG_RETENTION_BOOT_MODE=y CONFIG_REBOOT=y sysbuild.conf: SB_CONFIG_BOOTLOADER_MCUBOOT=y # use hci ipc as netcore child image SB_CONFIG_NETCORE_HCI_IPC=y # use netcore bootloader as child image # secure bootloader is required for netcore bootloader see: # https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/samples/nrf5340/netboot/README.html#building_and_running SB_CONFIG_SECURE_BOOT_NETCORE=y # secure boot on appcore doesn't seem to be required SB_CONFIG_SECURE_BOOT_APPCORE=n # required to update netcore image from appcore using mcuboot SB_CONFIG_NETCORE_APP_UPDATE=y # one image pair mode without scratch partition SB_CONFIG_MCUBOOT_NRF53_MULTI_IMAGE_UPDATE=n SB_CONFIG_MCUBOOT_UPDATEABLE_IMAGES=1 SB_CONFIG_MCUBOOT_MODE_SINGLE_APP=y # Match MCUboot signing type with keys/appcore_debug_mcuboot_private.pem (EC P-256) SB_CONFIG_BOOT_SIGNATURE_TYPE_ECDSA_P256=y my_board_nrf5340_cpuapp.overlay: I have a little bit change the way to reserve the byte for retention and I have aligned with the way we reserve the memory for the ipc service. The benefit is to be able to see the full sram memory inside partition_manager_report. / { chosen { ... zephyr,ipc_shm = &sram0_shared; zephyr,boot-mode = &boot_mode0; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; sram0_shared: memory@20070000 { /* SRAM allocated to shared memory */ reg = <0x20070000 0xFC00>; }; sram0_retained: memory@2007fc00 { /* SRAM reserved to retained memory */ reg = <0x2007FC00 0x400>; }; }; gpio_fwd: nrf-gpio-forwarder { compatible = "nordic,nrf-gpio-forwarder"; status = "okay"; /delete-node/ uart; // enable the array below in order to enable (debug-) UART on NetCore. // Note: if this is enabled, (debug-) UART on AppCore will not work anymore. // uart0 { // gpios = <&gpio1 5 0>, <&gpio1 4 0>, <&gpio1 7 0>, <&gpio1 6 0>; // }; netcore_led { gpios = <&gpio0 28 0>, <&gpio0 29 0>, <&gpio0 30 0>; }; }; sram0_retained@2007ffff { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2007ffff 0x1>; zephyr,memory-region = "RetainedMem"; status = "okay"; retainedmem { compatible = "zephyr,retained-ram"; status = "okay"; #address-cells = <1>; #size-cells = <1>; boot_mode0: boot_mode@0 { compatible = "zephyr,retention"; status = "okay"; reg = <0x0 0x1>; }; }; }; }; sysbuild/hci_ipc/boards/my_board_nrf5340_cpunet.overlay: reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; sram0_shared: memory@20070000 { /* SRAM allocated to shared memory */ reg = <0x20070000 0xFC00>; }; sram0_retained: memory@2007fc00 { /* SRAM reserved to retained memory */ reg = <0x2007FC00 0x400>; }; }; sysbuild/mcuboot.overlay: / { chosen { zephyr,console = &uart1; zephyr,shell-uart = &uart1; zephyr,uart-mcumgr = &uart0; zephyr,ipc_shm = &sram0_shared; zephyr,boot-mode = &boot_mode0; }; pmic { status = "disabled"; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; sram0_shared: memory@20070000 { /* SRAM allocated to shared memory */ reg = <0x20070000 0xFC00>; }; sram0_retained: memory@2007fc00 { /* SRAM reserved to retianed memory */ reg = <0x2007FC00 0x400>; }; }; sram0_retained@2007ffff { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x2007ffff 0x1>; zephyr,memory-region = "RetainedMem"; status = "okay"; retainedmem { compatible = "zephyr,retained-ram"; status = "okay"; #address-cells = <1>; #size-cells = <1>; boot_mode0: boot_mode@0 { compatible = "zephyr,retention"; status = "okay"; reg = <0x0 0x1>; }; }; }; }; sysbuild/mcuboot.conf: # serial recovery CONFIG_MCUBOOT_SERIAL=y CONFIG_BOOT_SERIAL_UART=y CONFIG_BOOT_SERIAL_ENTRANCE_GPIO=n CONFIG_BOOT_SERIAL_WAIT_FOR_DFU=y CONFIG_BOOT_SERIAL_WAIT_FOR_DFU_TIMEOUT=500 CONFIG_BOOT_SERIAL_NO_APPLICATION=y CONFIG_BOOT_SERIAL_BOOT_MODE=y CONFIG_BOOT_SERIAL_IMG_GRP_HASH=y CONFIG_UPDATEABLE_IMAGE_NUMBER=1 # Skip checks on the secondary image to make it possible to update MCUBoot on S1/S0 CONFIG_MCUBOOT_VERIFY_IMG_ADDRESS=n # increase speed of the serial CONFIG_BOOT_MAX_LINE_INPUT_LEN=4096 CONFIG_BOOT_SERIAL_MAX_RECEIVE_SIZE=4096 # boot mode retention CONFIG_RETENTION=y CONFIG_RETAINED_MEM=y CONFIG_RETAINED_MEM_ZEPHYR_RAM=y CONFIG_RETENTION_BOOT_MODE=y # serial recovery netcore CONFIG_BOOT_IMAGE_ACCESS_HOOKS=y CONFIG_FLASH_SIMULATOR=y CONFIG_FLASH_SIMULATOR_DOUBLE_WRITES=y CONFIG_FLASH_SIMULATOR_STATS=n CONFIG_MCUBOOT_SERIAL_DIRECT_IMAGE_UPLOAD=y CONFIG_NRF53_RECOVERY_NETWORK_CORE=y CONFIG_PCD_APP=y # Decrease memory footprint CONFIG_SIZE_OPTIMIZATIONS=y sysbuild/b0n.overlay: / { chosen { zephyr,ipc_shm = &sram0_shared; }; reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges; sram0_shared: memory@20070000 { /* SRAM allocated to shared memory */ reg = <0x20070000 0xFC00>; }; sram0_retained: memory@2007fc00 { /* SRAM allocated to shared memory */ reg = <0x2007FC00 0x400>; }; }; pmic { status = "disabled"; }; }; sysbuild/mcuboot_flash_sim_size.overlay: /* Keep flash simulator size aligned with netcore upload mediator partition * for nRF53 serial recovery in one-image-pair mode. */ &flash_sim0 { reg = <0x00000000 0x00038000>; }; &slot2_partition { reg = <0x00000000 0x00038000>; }; sysbuild/CMakeLists.txt: # Apply flash simulator size override after sdk-nrf's flash_sim.overlay has defined flash_sim0 add_overlay_dts(mcuboot ${CMAKE_CURRENT_LIST_DIR}/mcuboot_flash_sim_size.overlay) pm_static.yml: ## FLASH ## mcuboot: address: 0x0 end_address: 0xc000 placement: align: end: 0x1000 before: - mcuboot_primary region: flash_primary size: 0xc000 # This partition is used to align the app image to the old partitioning scheme padding: address: 0xc000 size: 0x1C000 region: flash_primary mcuboot_primary: address: 0x28000 size: 0x6c000 span: [mcuboot_pad, app] region: flash_primary mcuboot_pad: address: 0x28000 size: 0x200 region: flash_primary mcuboot_primary_app: address: 0x28200 size: 0x6be00 span: [app] region: flash_primary app_image: address: 0x28200 size: 0x6be00 span: [app] region: flash_primary app: address: 0x28200 size: 0x6be00 region: flash_primary mcuboot_secondary: # not necessary but was present on old partioning scheme address: 0x94000 size: 0x6c000 region: flash_primary mcuboot_secondary_1: # not necessary but was present on old partioning scheme address: 0xC0000 region: flash_primary size: 0x38000 settings_storage: address: 0xf8000 size: 0x8000 region: flash_primary ## SRAM ## mcuboot_primary_1: address: 0x0 size: 0x38000 device: flash_ctrl region: ram_flash pcd_sram: address: 0x20000000 size: 0x2000 region: sram_primary # rpmsg_nrf53_sram partition is not used at the compilation and is here only to reserve the memory for the RPMsg buffer. rpmsg_nrf53_sram: address: 0x20070000 # should correspond to the base address of sram0_shared reserved memory region in the DTS size: 0xFC00 # should correspond to the size of sram0_shared reserved memory region in the DTS region: sram_primary # sram_retained_mem_reserved is for now not used is only reserved memory for a future use of retained memory in SRAM sram_retained_mem_reserved: region: sram_primary address: 0x2007FC00 # should correspond to the base address of sram_retained reserved memory region in the DTS size: 0x3FF # should correspond to the size - 1 of sram_retained reserved memory region in the DTS # sram_retained_boot_mode is not use at the compilation and is here only to reserve the memory for the boot mode value sram_retained_boot_mode: region: sram_primary address: 0x2007FFFF # should correspond to the boot_mode0 node location in the DTS size: 0x01 # should correspond to the size of the boot_mode0 node in the DTS