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nRF240L01 with STM8L051F3

Hi, I am looking for procedure to make it work nRF240L01? I am getting documents for Arduino but as you know that is not understandable, with Arduino it worked but i don't understood. Now i want to make it work with STM8L051F3. STM8L051F3 is 8 bit ultra low power controller. I am looking for procedure like what steps i have to follow so i can send data to another nRF240L01. Which commands i have to send. I want to transmit data after every 1 sec and then it will go in power down. Receiver will be always in receiver mode.

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  • Thank yo very much for your reply

    I will do exactly as the example you sent an inform results in about 2 days

    I have well tested the SPI comunications , working OK

    ---------------------------------------------------------------

    Level compatibility with 5VuP VCC.

     I have measured  CE  CSN  MOSI  and they are OK about input levels for uP   Vcc = 5V)

    MISO output with 4K7  resistor to +5V  also has complete 0 an 5V range.

    For  IRQ  similar resistor to +5V has no effect. I didn't find this information in data sheet

    If uP has some problem with 3.3V as high level, I can reduce the Vcc supply to about 4V or add a small mosfet transistor as inverter (modifying as needed IRQ polarity definition)

    Regards, Osvaldo

  • Hi Osvaldo

    Sorry for the slow response, I was out in Easter vacation until today. 

    Are you still having issues with this? 

    The nRF24L01+ will only work in the 1.9-3.6V range, and it is important that you keep the supply and the interface signals within this range. 

    If you are unable to use an MCU that supports this level you will need some kind of level shifters on the signals, and a separate regulator for the nRF device to provide the supply voltage. 

    Best regards
    Torbjørn

  • Hi,

     

    Initially your regs look like this:

    addr + 0x20 content
    20 7A
    21 0
    22 1
    23 5
    24 0
    25 1E
    26 6
    2A E7E7E7E7E7
    2B E7E7E7E7E7
    2C E7
    2D E7
    2E E7
    2F E7
    30 E7E7E7E7E7
    31 20
    32 0
    33 0
    34 0
    35 0
    36 0
    3D 1

     Here RX_ADDR_P0 is equal to RX_ADDR_P1, which is not allowed:

    It does not matter if they are enabled or not, Pipe0 cannot be equal to Pipe1.

    Are these the readback status register?

    Dumping nRF24l01 registers
    
    0x00 A8 C8 E8 08 28 48 68 88 A8 C8 E8 08 28 48 68 88 
    0x10 A8 C8 E8 08 28 48 68 88 A8 C8 E8 08 28 17 

    I am also a bit uncertain what this data is:

    then so and so in a loop:
    
    FF 17 FF 17 FF 17 FF 17 FF 17 FF 17 FF 17 FF 17 FF 17 FF 17 
    FF 17 FF 17 FF 17 FF 17 FF 17 FF 

    The STATUS register shall never return 0xFF. 

    Kind regards,

    Håkon

  • Tusen takk for all comments so far.  I have made changes suggested, but still no receive between two separatre units.  However I am getting a packet received indication in my code when I transmit from each unit in its own receiver. Is it expected that if PTX and PRX have same address a unit will lreceive its own packets?   This would indocate progress to me!

  • Hi,

     

    Are you certain that you are using this command?

    That should be cmd=0xB0.

     

    VE3ID said:
    I have made changes suggested, but still no receive between two separatre units.  However I am getting a packet received indication in my code when I transmit from each unit in its own receiver. Is it expected that if PTX and PRX have same address a unit will lreceive its own packets?   This would indocate progress to me!

    Which event do you receive specifically here? If "NOACK" is used, a STATUS::TX_DS shall be set.

     

    Kind regards,

    Håkon

  • Thanks to all for the help I have had so far.  I am now able to send and receive complete packets, however, there is a terrible intermittency in my reading the status register to see if a packet has been sent out, sometimes it hangs on the <send 0x07> <listen for status including TX_DS> loop for many seconds!  I will try and include graphic of logic anal yser.

  • Hi,

     

    TX_DS should occur quickly, especially when using "W_TX_PAYLOAD_NO
    ACK", as shown in the PS chapter 7.5.1:

     

    If you have a stored logic trace of the SPI communication, I would be happy to have a look.

     

    Kind regards,

    Håkon

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