After enabling and starting the watchdog timer (RR0), how can it be disabled?
This following code does not work:
NRF_WDT->RREN &= ~(1 << WDT_RREN_RR0_Pos);
NRF_WDT->POWER = 0;
Edit: I'm using a Rev G0 chip.
I don't believe this is an errata item. Rather, it appears to be a designed in behavior. If you look at the Reference Manual (2.0) section 22.214.171.124 on reset behaviors, the WDT is preserved on a soft reset…
Can you please share the code of DFU with watchdog service
All I did was add a service of the WDT in the wait for events loop and also when the loop exits so that the WDT has its full amount of time while the system restarts. Just put this line in two spots in…
I haven't found a way to stop the WDT once it is started short of a power cycle. It even appears to continue to run after reset. I had to add a watchdog service to the DFU code to prevent WDT timeouts during bootloading.
I think I'm also seeing that behavior too (WDT still running after a SW reset).
Do you think this should be an errata item?
I don't believe this is an errata item. Rather, it appears to be a designed in behavior. If you look at the Reference Manual (2.0) section 126.96.36.199 on reset behaviors, the WDT is preserved on a soft reset. It requires one of the following reset types to be cleared on reset: power, pin, brownout or watchdog.
It could be more clearly stated in the watchdog section of the document as well, but it appears to be design intent.
Also note the following statement from the watchdog section of the reference manual: "The watchdog must be configured before it is started. After it is started, the watchdog’s configuration
registers, which comprises registers CRV, RREN, and CONFIG, will be blocked for further configuration. "
Once configured and started, the watchdog timer cannot be stopped, unless one hard reset (watchdog or power/brownout or reset pin) arrives.