This post is older than 2 years and might not be relevant anymore
More Info: Consider searching for newer posts

Custom board not seen by IOS device but it is seen by NRF-Connect Desktop

Hi There,

I've been developing a product using the NRF52DK.  I had some custom PCB's made after I had my circuit designed, and I programmed them with the NRF52DK.  Now my boards and the NRF52832 on the DK are running the exact same firmware.

With the NRF52DK, I can connect to my service on NRF Connect for IOS and Desktop (with an NRF51 dongle). 

With my boards, I can't see them with IOS (using NRF Connect or LightBlue) but I can see them using NRF Connect Desktop.  

When I scan with NRF Connect Desktop, my boards' RSSI indicates a fairly strong signal (~ -55dBm) and I can connect and view/control all the characteristics fine.  

I'm going to continue poking around to try to understand what's different but I'm quite stumped as to why IOS will only see the NRF52832 on the DK, but NRF Connect Desktop will see either the DK or the custom board.  I've tried an iPhone and an iPad and got the same result.

Any suggestions would be greatly appreciated!

Thanks,

Roger

Parents
  • Make sure you don't broadcast with an Apple manufacturer ID (ie, 0x004c).  iOS segregates all 0x004c broadcasts to the CoreLocation API's, only non 0x004c show up in the CoreBluetooth API's. 

    Or, if you are using CoreLocation in iOS then you can only broadcast with an Apple ID. 

  • Thank you for the suggestion, but I am fairly sure it's not an addressing issue since I can connect just fine using the same firmware on the PCA10040 DK.   

  • Please don't apologize, I'm willing to wait for free advice!  I hope your travels were pleasant.

    I added the upper layer ground pour and some stitching vias.  One change here compared to the first board was that I ensured that C25 only returned to the ground pad of the NRF as suggested in the product spec, which I'd neglected to do on V1.  

    When I started looking into buck converters with plans to use a single 3.7V battery, most of the ones I found suggest at least 500mV of headroom between source and output.  That means that if I wanted to use the entire range of the battery, my VCC would be well below 3V...I'm concerned about driving the Boost FET with that low of a gate drive, since the current FET's upper limit for VGSth is 3V.  Stacking two batteries gives me loads of headroom, allows for use of a proper gate driver on the boost and will let me drop the DC on the boost drive.  It's a bit of a tradeoff on cost to include two batteries, but I think it's worth it for the points mentioned above.

    If I continue to run into RF issues with this board, I am considering moving this to a Rigado module, leaving the RF stuff to people who know what they're doing while maintaining a small footprint.  The additional benefit of that route is a relatively easy transition to an NRF52840 in the future if I determine that I need the additional range offered by BLE 5, which is a serious concern of mine.

    Files2V2.zip

  • Vias should always flood over vias (ie, no thermals) especially when they are used to get rid of heat as in your LED.  The only time thermals should be applied to a via is when it is a thru-hole part then it is done to aid soldering.

    Actually thru-holes and vias are normally treated as two different model types in most cad packages since in addition to thermals, the annular ring will be different.

    Similarly you should not thermal the heat relieving pads on your led for the same reason.  The only reason thermals get used on SMT is to help prevent tombstoning.  This won't be an issue for your led as the ground pads are massive compared to the signal pads.

  • I don't know what the purpose of SOL_SNS is but even with D2, I would be concerned about the back emf from the solenoid being large enough that you could damage the nRF. It will take a few nsec for D6 to turn on and in that time the reverse voltage could easily be over 20 volts, maybe more.

    For similar reasons you should use something other than the DMP1045U. The spec shows a max Vds of 12V.  This should be a 50-100v part.  That back emf will be massive from the solenoid.  Also, to reduce the back emf, D6 should be a schottky and there should be a 100 volt chip cap across D6.  Maybe a 1206 package so you can get the value right later. It doesn't need to be a big cap it just picks up the slack until the schottky turns on.

    If you want to have some math fun you can find the inductance and Rdc for the solenoid and then calculate the peak voltage when you turn it off for your cap/schottky combo.

    If SOL_SNS is to figure out when the solenoid has reach steady state, then you should do it another way.  The boost converter will just increase the duty cycle as the current builds in the solenoid.  Ideally at D2 you will just see a steady Vsolenoid nothing more. A safe easy approach would be a fat resistor on the ground return for the solenoid and monitor the voltage build with the nRF. There are plenty of cheap small ohm value resistors like that since they get used for the feedback in DC/DC converters. If you don't want to use the SAADC to monitor then choose a resistor value that will trip the CMOS to logic high.

  • You should always pin out nReset to the SWD.  This shows up a lot on the devzone.  Your code can keep the SWD from initializing. If makes debug a real pain when this happens since holding the nRF in reset is the only way to fix the problem.

    The J-link does does a pin reset in addition to issuing a reset command via SWD during programming.

    Also you might find it easier using the standard 10 pin header that the programmers normally have.  This makes the hookup easier since you don't have to make your own cables.

    R5 is pointless since the nRF has internal pullups.

  • I was going to use SOL_SNS just to determine whether or not the solenoid is present before enabling the Boost.  The plan is to use a pull-up in the NRF and then read it.  If the low resistance of the solenoid is present, I'll detect a low input voltage of D2's Vf.  If the solenoid isn't present then I'll see a hi-level and won't enable the Boost.  You're probably right that it would be worthwhile to put some protection on the nRF side....If nothing else, a little RC between the nRF and the anode of D2 would hopefully catch anything that got through D2...That circuit is only measuring DC voltage prior to enabling the boost, so I could put a pretty big C there and 100 ohms between nRF and the C to hopefully snub anything out.

    I'm hoping that I won't have too many issues with back-emf due to not switching the solenoid...If I was driving it with a low-side switch then I'd be more concerned, but I was thinking that things would be relatively graceful with this design, and that Q1 would never see much VDS due to it floating up with the boost output.  

Reply
  • I was going to use SOL_SNS just to determine whether or not the solenoid is present before enabling the Boost.  The plan is to use a pull-up in the NRF and then read it.  If the low resistance of the solenoid is present, I'll detect a low input voltage of D2's Vf.  If the solenoid isn't present then I'll see a hi-level and won't enable the Boost.  You're probably right that it would be worthwhile to put some protection on the nRF side....If nothing else, a little RC between the nRF and the anode of D2 would hopefully catch anything that got through D2...That circuit is only measuring DC voltage prior to enabling the boost, so I could put a pretty big C there and 100 ohms between nRF and the C to hopefully snub anything out.

    I'm hoping that I won't have too many issues with back-emf due to not switching the solenoid...If I was driving it with a low-side switch then I'd be more concerned, but I was thinking that things would be relatively graceful with this design, and that Q1 would never see much VDS due to it floating up with the boost output.  

Children
Related