Problem using the nRF52840 to interface an ADS1298 via SPI

Question

Hi DevZone, I am using the nRF52840 to interface an ADS1298 (ECG Chip) via SPI. 
 
 I want to test if the communication between the devices are working by: 
 - Sending a RREG (Read From Register) opcode from the nRF52840 to the ADS1298 
 - And then read its ID Register. 
 
 The RREG command is two bytes long, and for multi-byte commands the following needs to be done: 
 1. Send the first byte and then wait for 4 * tCLK before sending the next byte. 
 2. The CS (or SS) pin needs to be held low during the entire session for both transfer and receive.

I am trying to test this with the example provided in the nRF5 SDK 15.3 by using this function: 
 - nrf_drv_spi_transfer(&spi, m_tx_buf, m_length, m_rx_buf, m_length);

My problem is that: 
 - I cannot insert a delay between the bytes when using the nrf_drv_spi_tranfer() for multiple byte transfers 
 - If i use separate calls of the nrf_drv_spi_transfer() for each byte, then the CS pin is not held low. 
 Is there any way I can use this driver to send multiple bytes with a fixed delay between them, without the CS pin going high during the session? 
 
 Thank you for reading 
 Br. Casper

haakonsh · Accepted Answer

I suggest you scope the ADS1298's power supply line for any fluctuations or noise during startup. 
 From 9.5.2: NDS Enable Read Data Continuous mode. RDATAC 0001 0000 (10h) — This mode is the default mode at power up.(1) (1) When in RDATAC mode, the RREG command is ignored. From 9.5.2.10: When the device is in read data continuous mode (RDATAC), it is necessary to issue a SDATAC command before a RREG command can be issued. 
 From 11.1: Allow time for the supply voltages to reach their final value, and then begin supplying the master clock signal to the CLK pin . Wait for time tPOR, then transmit a reset pulse using either the RESET pin or RESET command to initialize the digital portion of the chip. Issue the reset after tPOR or after the VCAP1 voltage is greater than 1.1 V, whichever time is longer. Have you made sure that the clock signal is applied exactly when it's supposed to?

hmolesworth · Answer

Are you using SPI mode 1 and MSB first? The 'scope pictures are a little unclear, maybe displace the waveforms slightly from each other (vertically) so they are easier to read. This setup works: 
 nrf_drv_spi_config_t spi_config = NRF_DRV_SPI_DEFAULT_CONFIG;
 ret_code_t err_code;

 spi_config.ss_pin = ADS_CS_PIN;
 spi_config.miso_pin = ADS_MISO_PIN;
 spi_config.mosi_pin = ADS_MOSI_PIN;
 spi_config.sck_pin = ADS_SCK_PIN;
 spi_config.frequency = NRF_DRV_SPI_FREQ_500K; // Ensure less than 4 clk cycles for ADS1292
 spi_config.bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
 spi_config.mode = NRF_DRV_SPI_MODE_1;
 APP_ERROR_CHECK(nrf_drv_spi_init(&mAfeSpiInstance, &spi_config, afe_spi_event_handler, NULL)); 
 However as you are going off-board with the signals, I would suggest start with enhanced drive on SCK, MOSI and CS. The traces above may look clean, but fast jitter on the edges are not visible at this 'scope resolution, and edge jitter can corrupt expected transactions, notably on SCK. Add this after spi init: 
 // High power output pins to ensure clean edge transitions off-board
 nrf_gpio_cfg(ADS_SCK_PIN
 NRF_GPIO_PIN_DIR_OUTPUT,
 NRF_GPIO_PIN_INPUT_DISCONNECT,
 NRF_GPIO_PIN_NOPULL,
 NRF_GPIO_PIN_H0H1, // Test with High Drive high and low level
 NRF_GPIO_PIN_NOSENSE);

hmolesworth · Answer

You don't necessarily need to add a delay, just to conform to the AFE requirements. 
 // Sending Multi-Byte Commands
// The ADS1291, ADS1292, and ADS1292R serial interface decodes commands in bytes and requires 4 tCLK cycles
// to decode and execute. Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of
// one byte (or opcode) and the next.
// Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 us. When SCLK is 16 MHz, one byte can be
// transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be
// inserted so the end of the second byte arrives 7.3125 us later. If SCLK is 1 MHz, one byte is transferred in 8 us.
// Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
// delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to
// multiple bytes.

 spi_config.frequency = NRF_DRV_SPI_FREQ_500K; // Ensure less than 4 clk cycles for ADS1292/8 
 Since transfers are only a few bytes, typically the slower clock speed is not an issue. Other issues tend to be more problematic; as an example the internal AFE clock has drift with respect to external timing sources, such as the crystal-clocks used further down the chain in ECG analytics. This has to be handled without introducing artifacts in the ECG stream. 
 Using an external crystal clock is only one option to minimise this, but as a tip note that without a clock the ADS129x AFE is unavailable via SPI. So if the clock select pin is set to external clock mode the SPI interface will simply not work until the external clock is present. A classic mistake is to use the AFE output pin to select the clock source, which if defaulted to external (via a pull-up) means first an external clock has to be supplied to allow SPI transfers, then the pin programmed low for internal clock via SPI, then the external clock can be removed again. 
 To manually control the CS pin, set the pin to not used; this is the nrf example, but may differ slightly depending on which library versions you are using 
 spi_config.ss_pin = NRF_DRV_SPI_PIN_NOT_USED

hmolesworth · Answer

You may be overlooking the following; I think all family members start up in the read-continuous mode: 
 " If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. " 
 AdsReset(); // Reset ADS - not necessary if using power-on reset
 AdsSendCmd(ADS_CMND_SDATAC); // Stop continuous mode
 // Turn on internal reference and allow time to settle
 AdsWriteReg(ADS1x9x_REG_CONFIG2, 0xA0);
now read id .. 
 Otherwise the command looks correct: 
 /****************************************************************/
/* ADS1x9x COMMAND DESCRIPTION and definitions */
/****************************************************************/
typedef enum {
 // System Commands
 ADS_CMND_WAKEUP = 0x02, // Wake-up from standby mode
 ADS_CMND_STANDBY = 0x04, // Enter standby mode
 ADS_CMND_RESET_CMD = 0x06, // Reset the device registers
 ADS_CMND_START = 0x08, // Start/restart (synchronize) conversions
 ADS_CMND_STOP = 0x0A, // Stop conversion
 ADS_CMND_OFFSETCAL = 0x1A, // Channel offset calibration - needs to be sent every time there is a change to the PGA gain
 // Data Read Commands
 ADS_CMND_RDATAC = 0x10, // Enable Read Data Continuous mode.
 // - This mode is the default mode at power-up.
 ADS_CMND_SDATAC = 0x11, // Stop Read Data Continuously mode
 ADS_CMND_RDATA = 0x12, // Read data by command; supports multiple read back.
 // Register Read/Write Commands
 ADS_CMND_RREG = 0x20, // Read n nnnn registers starting at address r rrrr
 // - first byte 001r rrrr (2xh)(2) - second byte 000n nnnn(2)
 ADS_CMND_WREG = 0x40 // Write n nnnn registers starting at address r rrrr
 // - first byte 010r rrrr (2xh)(2) - second byte 000n nnnn(2)
} ADS1x9xCommand_t;
 
 I should add that if you are going off-board to the ADS development board it might be necessary to boost the drive to SCK, CS and MOSI pins from S0S1 to H0H1 after the SPI has been initialised; not usually necessary at lower SCK speeds however..

Problem using the nRF52840 to interface an ADS1298 via SPI

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