GPIO setup parameters for AoA Antenna switching

I have an issue with getting the I/Os correctly setup for antenna switching.

I am running the radio_test example code with the following modifications. 

So far, I have the following code for the GPIO setup:

//Defines are at top of file
#define ANT1 NRF_GPIO_PIN_MAP(0,17)
#define ANT2 NRF_GPIO_PIN_MAP(1,8)
#define ANT3 NRF_GPIO_PIN_MAP(1,7)
#define ANT4 NRF_GPIO_PIN_MAP(1,6)

//other support code

//Pin config
nrf_gpio_pin_clear(ANT1);
nrf_gpio_cfg_output(ANT1);
nrf_gpio_pin_clear(ANT2);
nrf_gpio_cfg_output(ANT2);
nrf_gpio_pin_clear(ANT3);
nrf_gpio_cfg_output(ANT3);
nrf_gpio_pin_clear(ANT4);
nrf_gpio_cfg_output(ANT4);

//DFE pin config
NRF_RADIO->PSEL.DFEGPIO[0] = ANT1; //(P0.17)
NRF_RADIO->PSEL.DFEGPIO[1] = ANT2; //(P1.08)
NRF_RADIO->PSEL.DFEGPIO[2] = ANT3; //(P1.07)
NRF_RADIO->PSEL.DFEGPIO[4] = ANT4; //(P1.06)

NRF_RADIO->SWITCHPATTERN = 1; //Only P0.07 active
NRF_RADIO->SWITCHPATTERN = 2; //Only P1.08 active
NRF_RADIO->SWITCHPATTERN = 4; //Only P1.07 active
NRF_RADIO->SWITCHPATTERN = 8; //Only P1.06 active

NRF_RADIO->DFEMODE = RADIO_DFEMODE_DFEOPMODE_AoA;
NRF_RADIO->DFECTRL1 = 10 << RADIO_DFECTRL1_NUMBEROF8US_Pos | 
                       1 << RADIO_DFECTRL1_DFEINEXTENSION_Pos;

Then in the radio_test.c file, I include in the function radio_rx( ...)

uint32_t g_iq_packet[RADIO_MAX_PAYLOAD_LEN];

void radio_rx(....)
{
//orig example code still exists here, only not shown
    NRF_RADIO->DFEPACKET.PTR = (uint32_t)g_iq_packet;

}

From a board running the radio_test example, I issue the 'start_tx_modulated_carrier' command the immediately issue the 'start_rx" command on a seperate DK also running the radio_test example with the above modifications.

I expected to see a short duration square wave on each of the antenna GPIO pins, so, 4 square waves cascading in time. However from my logic analyzer capture, you can clearly see that is not the case.

How should I be setting up the config registers to fire each of the pins.  Nothing else is connected to the board except the logic analyzer.

Also, how do I correlate the IQ data from the DFEPACKET.PTR to the specific antenna?

Parents
  • A result of some tests:

    I have my configuration as follows:

    NRF_RADIO->DFEMODE = RADIO_DFEMODE_DFEOPMODE_AoA;
    NRF_RADIO->DFECTRL1 = 3 << RADIO_DFECTRL1_NUMBEROF8US_Pos | 
                           1 << RADIO_DFECTRL1_DFEINEXTENSION_Pos |
                           3 << RADIO_DFECTRL1_TSWITCHSPACING_Pos |
                           1 << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos |
                           3 << RADIO_DFECTRL1_TSAMPLESPACING_Pos ;
    
    
    NRF_RADIO->CTEINLINECONF = 1 << RADIO_CTEINLINECONF_CTEERRORHANDLING_Pos |
                               0 << RADIO_CTEINLINECONF_CTEINFOINS1_Pos;

    Which gives me a response on the RX side as the following:

    Received payload:
    Buffered IQ Samples:14
    Data0: -130, 26624, 
    Data1:  -157, 9216, 
    Data2:  -96, 30208, 
    Data3:  -13, -768, 
    Data4:  1, -2816, 
    Data5:  -117, 29440, 
    Data6:  -11, 17664, 
    Data7: 1, -5376, 
    Data8:  5, -2560, 
    Data9:  -11, 17152,
    Data10: 70, 22016,
    Data11: 12, -4864,
    Data12:  5, -1536, 
    Data13:  54, 19456

    The first number is the I and the second is the Q.  With how I have the RX side configured, my NUMBEROF8US is 3, meaning I have 24uS total. The TSAMPLESPACINGRED is set to 4uS ann my TSAMPLESPACING and TSWITCHSPACING is set to 1uS intervals.

    I dont understand how I am getting 14 IQ samples. If I am getting 2 samples in my REFERENCE period, that would leave 12 samples for IQ. but then that would mean my my total time is  4uS (guard band) + 8uS (reference) + 12uS(Sample time) + 12uS ( Switching time) = 36uS.  

    Can you help shed light?

    Thanks!

  • Are you setting NRF_RADIO->DFEPACKET.MAXCNT  and then checking NRF_RADIO->DFEPACKET.AMOUNT before grabbing the samples?

  • So, than means we get samples not only in the sample slot, but also in the switch slot, right? That's not really clear from the documentation...

    Yes, you get 8 usec of continuous sampling for the reference period, then 1 usec gap, then again continuous sampling.

  • Dmitry,  We see that the  first 8 usec is the reference period. What Bruno is asking is if the sampling is still happening and outputting data while switching is happening. If it IS happening, then we would need to know to be able to account for that extra data in the datastream.

  • Yes, as I wrote, there is continuous sampling after the gap - sample data is present for switching periods too. 

  • Hi there, 

    Sorry for answering here (or joining the discussion), but I can't answer directly for first message in the thread. 

    I hope information below will add something to the discussion and improve understanding what is going on about I/Q samples.

    Below is your configuration of radio:

    NRF_RADIO->DFEMODE = RADIO_DFEMODE_DFEOPMODE_AoA;
    NRF_RADIO->DFECTRL1 = 3 << RADIO_DFECTRL1_NUMBEROF8US_Pos |
    1 << RADIO_DFECTRL1_DFEINEXTENSION_Pos |
    3 << RADIO_DFECTRL1_TSWITCHSPACING_Pos |
    1 << RADIO_DFECTRL1_TSAMPLESPACINGREF_Pos |
    3 << RADIO_DFECTRL1_TSAMPLESPACING_Pos ;

    That means you have:

    1. 3*8us = 24us for duration of whole CTE

    2. sampling in the reference period is set to be 4us

    3. antennas are switched every 1us (in switching period, after reference period). That meas "switch slot" is 500ns and "sample slot" is 500ns

    4.  sampling in switch period is 1us.

    Total time of CTE is 28 us. Guard time is 4us. That period does not contribute to samples, so we have left 20us of time when some samples are taken. 

    Ref. period is 8us long and has 4us sampling time, so it gives us 2 samples.Also it leaves us with 12us for switching period.

    Switching period has set 1us sampling and gives us 12 samples. 

    Total 2 samples from ref period + 12 samples from switch period gives 14 samples. The value read from the NRF_RADIO->DFEPACKET.AMOUNT register.

     

    One more thing related with mapping of antennas to samples. In all diagrams there is an information that after reference period there is a switch-slot/sample-slot pairs sequence. Unfortunately there is a gap. The gap lasts for single switch-slot. So first sample you receive is taken in first sampling-slot. After that each sample is stored in configured delay. 

    That does matter for mapping of antennas to samples, especially in case of oversampling. 

    Let take for example following settings:

    • NUMBEROF8US=3 ->24us
    • TSWITCHSPACING=2us
    • TSAMPLESPACING=250ns
    • TSAMPLESPACINGREF=250ns

    Number of samples would be: Ref period 8us/0.25 = 32, switch-period 12/0.25=48

    First sample from switch-period would be taken in first sampling slot, so you would have a time delay of 4 samples (1us - swtich slot).

    After that delay you would have samples: 

    • 4 samples taken in 1st sampling-slot (antenna 1)
    • 4 samples taken in 2nd switch-slot (antenna 2)
    • 4 samples taken in 2nd sampling-slot (antenna 2)
    • 4 samples taken in 3rd switch-slot (antenna 3)
    • ....

    Samples taken during switch slot are not reliable so they should be discarded. 

    I hope that would help in understanding the topic.

  • Hi Dmitry,

    I'm struggling to understand how you have so many sample points between phase cycles (83-84?). What parameters are you using?

    Cheers

    Pete

Reply Children
  • Hi Pete,

    that diagram is with two antennas, 0.125us sampling interval and 2us/2us sample/switch slots - we have 8us (64 samples) between same points in cycle.

  • Hi Dmitry,

    Thanks. What mode (1Mbps or 2Mbps) are you using? I'm confused, as the phase must surely cycle over either 4us for a 250 kHz tone (1Mbps mode) or 2us for a 500 kHz tone (2Mbps mode). Or, with 0.125us sampling, 32 samples for 1Mbps or 16 samples for 2Mbps mode. Where does 8us come from?

    Your phase changes are much cleaner than mine. My phase phase looks like this, which I've posted in a new question: 

    My RF switch ought to be fast enough. Something is not right.

  • Hi Pete,

    I'm using 1Mbps, one of my boards seems to have low-quality crystal (a -50ppm error would give -120kHz frequency offset at 2.4Ghz, that's near my case).

    From your diagram, your switching time is about 1.2 usec, that's sufficient even for 2usec switching period - I don't see any problem here. Check whether you've set controlling GPIOs to high-drive mode.

  • Pete,  for what its worth, I see stuff similar to you. What is your hardware setup?

Related