Simple SPI

[verulia]

Hello,

I am using nrf9160 and want to test the just simple SPI function. The code that I found from github(https://github.com/Rallare/fw-nrfconnect-nrf/tree/nrf9160_samples/samples/nrf9160/spi c) is old and gives me too many errors. Are there any simple SPI code that I can try in my nrf9160 board in order to test whether I can send a simple data via SPI. I also found spi_flash_at45 however I don't have any device from at45 family to test it so another simple example would be so helpful for me. 

Thank you

[Håkon Alseth]

Hi,

 

Generic test code for nRF5340 can be found here:

https://devzone.nordicsemi.com/f/nordic-q-a/67065/how-to-configure-and-setup-an-spi-device-to-nrf5340/276687

 

I added some small modifications to the above sample, as SPI0 is shared with UART0/TWIM0 etc on nRF9160:

4520.simple_spi_test_nrf9160.zip

 

Kind regards,

Håkon

[verulia]

Hi,

Thank you for the fast reply. I just ran the code however I am always receiving 0 in the RX_recv. Shouldn't the value in RX_recv be similar with TX_sent since this code is just tries to send a value and receive it back as far as I understood? I didn't make any change in the code yet.

Q2:

I want to send data from nrf9160 to an external device, in order to just make a simple test before implementing a flash driver, I want to test the pins and spi, for that I am using scana to check the signals coming from spi ports. My question here is that how can I send my data to scana rather than making a loopback. For instance first I have to ad a chip select for scana, adding ss=<13> to the overlay file can be the first step right? What should I change other than this?

Thank you

[verulia]

Hi Hakan,

The pins are changed no problem in that part rigth now but still I can't see the rigth signal in the logic analyzer. I adjusted edge triggering with rising edge( also tried with falling and all other triggering options) I see that clk signal seems always high. Not 0-1-0-1 its always one.I played with sampling frequency but it also didn't change the result. I tested the logic analyzer with different chip and I saw 1-0-1-0 clk signal so logic analyzer is working fine. I didn't change the code that you sent me and it is doing loopback so no problem in spi functionality. Then what should I do in this case? I just want to see the clk signal and mosi in this case I thought that just attaching the logic analyzer to those output pins was sufficient to see the outputs am I missing something in this point?

Thank you

[verulia]

Hi, I couldn't get an answer for my last reply do you have any idea of what can I also try?

Thank for the help so much

[Håkon Alseth]

Hi,

 

On the UART terminal (serial terminal), are you getting the expected output when connecting MISO to MOSI using a patch wire?

ie: 

TX sent: X

RX recv: X

 

BR,

Håkon

[verulia]

Hi,

Yes when I connect miso to mosi with a wire I receive the same value. I also changed the gpio pins for clk and miso it also works fine when I change them I can still see the outputs on lte link monitor. The only problem is I cant even see the clk ouput 1-0-1-0 on logic analyzer, I also cant see mosi. The clk pin always gives 1 in logic analyzer but it should be 0-1-0-1. I changed the sampling rate, frequenct however still result is same. I didn't understand what I am missing. Should I have to make additional changes in the code or should I need to do some adjustments in the logic analyzer. But in logic analyzer when I just send 1-0-1-0 from gpio pins(different from spi pins) I was be able to see the output clearly without doing any modification

Thank you

[Håkon Alseth]

Hi,

 

verulia said:

Yes when I connect miso to mosi with a wire I receive the same value. I also changed the gpio pins for clk and miso it also works fine when I change them I can still see the outputs on lte link monitor. The only problem is I cant even see the clk ouput 1-0-1-0 on logic analyzer, I also cant see mosi.

If you are not able to view the data on your logic analyzer when looking at MISO, but the serial output shows that it sends for instance 10 and receives 10 when you connect MISO to MOSI, then the pin itself does toggle.

It is then a problem with your logic analyzer PC setup.

 

Kind regards,

Håkon

[verulia]

Hi Hakan,

Thanks for the reply. This issue is kind of important for me hence I need to solve it. Did you try the code that you sent me "this simple spi loopback", with logic analyzer? Can you see the clock output and the miso properly from the logic analyzer? Seeing the spi functionality from logic analyzer is very important for me to move on in my project. Also if you are able to see it from logic analyzer can you tell me your settings in the system such as sampling freq etc.

Thank you for the help

[Håkon Alseth]

Hi,

 

Yes, it seems to toggle at my end:

 

verulia said:

Can you see the clock output and the miso properly from the logic analyzer?

 MISO is the "master in, slave out", so unless you have anything externally connected to the device, it will not show anything. This is why I asked if you have connected the MISO signal to the MOSI signal. This is a loopback test.

 

Can you please confirm which pins aren't working, as per my former response?

Is it only the CLK pin not outputting a signal? Please provide a screenshot of your sampled signal.

Can you please share your current project so I can try it at my end?

 

Kind regards,

Håkon

[verulia]

Hi Hakan,

This is the output right now. MISO AND MOSI are connected together on the nrf. clk pin is 11. I only connected clk pin<11> to logic analyzer on CH2. My sampling rate is 1 MHz rigth now. When I increase the sampling rate I only see high(1) on CH2. The code that I am using is the one in the attachment I didn't change anything in that code. Once I get this observation work I will modifiy the code and move on. I am sure that logic analyzer is working because when I toggle the pins manually I can properly observe it. I was also be able to observe the clock signal with different microcontroller(nor nrf)

Thank you.

[verulia]

Also this is the output on lte link monitor when I connect MISO TO MOSI:

so it seems there aren't any problem in loopback test functionality.

[Håkon Alseth]

Hi,

 

Are you able to test with 1.8V setting in your logic analyzer SW? If you're using the nRF9160-DK, its default setting is 1.8V (changeable to 3.0V via the VDD_IO switch near the power switch).

 

Kind regards,

Håkon