Code Corrupted after full discharge of batteries, upon reboot. NRF51822 SDK 12.3

[Robin]

Hello Nordic Wizards,

We are in the final throws of a project preparing to go to market.  However we have identified a "strange" problem.

if the batteries driving the board power are allowed to fully discharge, once they start recharging, plugging/unplugging the board from a charger resets the board and may lock the code up in an unknown state.  If the board is reprogrammed, this condition stops, until the next time the battery/board is fully discharged.  Has anyone see these types of problems with this chip, and/or can you point me to a prospective solution.

Thank you kindly

Robin @ TL

[daviddedwin]

1. Please state the chip markings on the nRF51822
2. You should try this on an additional board if that is possible.
3. Read the flash on the chip after a failure to see if there is any difference before and after the condition occurs, the nrfjprog utility will help you read the chip flash.

[Robin]

Hello David,

I assume you are the assigned Nordic Engineer, No?  Anyway

The chips are marked "N51822/QFAAH3/1906EP.

The symptoms occur on all boards (10 each).

I will likely need some help using the nrfjprog utility.

One of our US field agents is suspicious of power circuit issues.  We are running the board/chip at 2.8V, with a precision 2.048V Ref applied to AIN0.   Can you please enumerate the settings I need to insure are correct for proper power management to occur?

Thank you kindly,

Robin @ TL

[Kenneth]

if the batteries driving the board power are allowed to fully discharge, once they start recharging, plugging/unplugging the board from a charger resets the board and may lock the code up in an unknown state.

A few things come to mind. Likely the internal power en reset does not trigger as expected. Do you have any measurement on the time to ramp up VDD during charging? There is a max 60ms rise time I believe allowed by spec. 

Are all GPIOs also low level while VDD is discharged? Just checking that the chip is not partially powered through a pin before VDD rise above minimum operating conditions again.

Does adding a 1Mohm resistor between nRESET and GND have any impact on the issue? 

Best regards,

Kenneth

[Robin]

Hello Kenneth,

No measure on VDD ramp up rate.  I would think (hope) there were a comparator that held off ops until well above the chip min op voltage.  Never seen a spec like that on a chip this sophisticated before.  But, the board should be up within a 200 uSec based on regulator and cap specs.

If batt/board are dead, can gpios be high?

Haven't tried nReset resistor as we are using the pin as SWDIO to program the chip, and is no such component on the reference design circuit we have from Nordic.

[daviddedwin]

I am not the assigned Nordic engineer, definitely looks like a power side issue and the power ramp will need to be looked at as Kenneth says.
I would also check the state of the flash after the battery is drained and see if its is ok and the state of the flash after you plug in, the easist way seems to be to use the nrfjprog --verify to verify the flash contents to the hex file flashed in. The board will need to have the jlink connected to the SWDIO lines to do this.

nrfjprog is part of the nRF Commandline tools https://www.nordicsemi.com/Products/Development-tools/nrf-command-line-tools