understanding the concept of INTENSET and how it's used along with NVIC for configuring interrupts

[morpho]

Trying to understand how interrupts work on nRF52: does setting an INTENSET register of the said peripheral enable the interrupt, and to propagate the interrupt over the Cortex M4, the NVIC_ISERx register needs to be set as well?

Is the idea similar to the depiction below where INTENSET is a part of the EXTI?

[Susheel Nuguru]

Settings the INTENSET in the peripheral level will enable or disable the interrupt at the source (peripheral) and the NVIC is on top of that which you normally enable or clear. If INTENSET bit is set for the peripheral which is generating interrupts and the NVIC level bit is not set, then you normally see that there is a pend bit set for this interrupt line when the peripheral generates interrupt but the Cortex does not process it yet due to your NVIC settings. You need to set the NVIC_ISER normally using CMSIS API.

In short, INTENSET at peripheral controls the source of the interrupt where as NVIC tells the Cortex to mask/unmask this interrupt processing.

[morpho]

Thanks. So if we were to map this in the diagram I shared above, it would be INTENSET setting the corresponding bit in EXTI? If not, is there any block diagram to illustrate the flow better?

[Susheel Nuguru]

Not sure if there is any representation available in that way but it is something like this

You need to

1) configure the peripheral and enable it
2) Enable the relevant bit in the INTENSET for that peripheral so that i can generate interrupt that can be sent to ARM_NVIC

3) Enable the interrupt bit in the NVIC (look at ARM documentation for this)

[morpho]

Fair. Instead of EXTI, nRF seems to have INTENSET register for enabling a certain peripheral

[Susheel Nuguru]

yes, that is correct comparison.