TIMER1 compare not triggered for CC=0x00

[Nick]

I am using a TIMER1 compare event to generate an interrupt. Generally the code all works fine, but I have noticed some strange behaviour when loading the CC register with 0x00. If the timer is allowed to run freely and overflow, then it is possible to generate a compare event when the timer rolls-over to 0. No problem there. But then I tried to limit the maximum timer count using;

NRF_TIMER1->SHORTS |= TIMER_SHORTS_COMPARE2_CLEAR_Enabled << TIMER_SHORTS_COMPARE2_CLEAR_Pos;
NRF_TIMER1->CC[2] = T1_TICKS_MAX;

My understanding is that this should cause the timer to reset to zero when it hits the value in CC2 (T1_TICKS_MAX). However, when I do this I no longer get any compare events generated for CC=0x00. Any other CC value less than or equal to T1_TICKS_MAX works fine.

This seems a bit unexpected to me. Is this normal behaviour? Or do I perhaps have a bug in my code somewhere?

[Susheel Nuguru]

I am not sure what you are trying to achive here. Why do you need SHORT to clear timer in this case? What is the value of T1_TICKS_MAX? if it is 0XFFFF Then you do not need that short, it will overflow and the next counter value will be zero anyway.

If you enable clear_short at 0XFFFF, i think the short logic conflicts with the event logic at the same HFCLK cycle and looks like the event is missed. In my opinion, this is expected to be unpredictable in this case.

[Nick]

I see what you mean. Thanks for the suggestion. But I think there are a couple of issues that will complicate this solution.

First, it requires me to update multiple register values while the timer is running. In an ideal implementation all the CC registers (including ones that are used for scheduling and to set the roll-over value) would be updated atomically, within a single clock cycle. But in reality I can't achieve this and some registers will be updated before others. If I decrease the roll-over CC register before increasing (with modulo) the scheduler CC register then I run the risk of missing the compare event. If I update the registers in the reverse order then I run the risk of getting two compare events.